FinFETs have begun to replace traditional planar transistors in next generation electronic devices due to the ability to enhance the control of current flowing between source and drain regions of the transistors at smaller nanometer nodes. Devices, such as memory structures, also benefit from the use of FinFETs because FinFETs have lower power and provide increased transistor density while enabling improved device performance.
Memory structures that use FinFETs remain susceptible to single event latch-ups (SEL), just like planar transistors. Latch-up in CMOS technologies is caused by the triggering of a parasitic p-n-p-n SCR (silicon controlled rectifier) structure. SEL is caused by transient currents originating from charges generated along the track of an incident charged particle. Neutrons are the primary cause of SEL in terrestrial applications. Conventional SEL mitigation techniques for planar transistor aim to decouple or weaken elements of the parasitic SCR structure. Such techniques are typically associated with an area penalty that can be tolerated for a given application. Until recently both CMOS and underlying SEL device physics have scaled together in planar transistors, thus allowing predictable SEL results for a given design flow. However, this has changed with the recent introduction of FinFET technology as it has been observed that the failure rate associated with SEL events in FinFETs is generally higher than that of planar transistors.
Thus, there is a need for an improved FinFET.